Analysis of circuit parameter variations in discrete clock driver designs for high capacitive load detectors for space applications

High Capacitive Load Detectors like linear/array or TDI (Time Delay and Integration) CCDs (Charge Coupled Devices) are inevitable in modern day high resolution satellites. These detectors require clocks with stringent constraints like fast rise/fall times and large high/low voltage levels. As no off the shelf drivers are available, these requirements are to be met by discrete clock drivers. These drivers are required to provide parallel and serial register clock signals for reading out the stored charges in the MOS (Metal Oxide Semiconductor) gates to final output stage of the detector. High speed clocking due to sub meter resolution imaging calls for precise design for these clock drivers. The degradation in design parameters can affect the charge transfer efficiency. The circuit parameters of this design play a very critical role in the performance of the clock driver circuit. This paper discusses the various parameters that effect the performance of the circuit & presents simulations& analysis for the same.