A New Figure of Merit Equation for Analog-to-Digital Converters in CMOS Image Sensors

This paper presents a new figure-of-merit (FoM) equation for column analog-to-digital converters (ADCs) in CMOS image sensors. The proposed FoM incorporates the dynamic range, resulting from the minimum dark-level random noise and the maximum full well capacity, as well as AD conversion time, power consumption, and area. Using this FoM, we have analyzed various ADC architectures including cyclic, delta-sigma, successive approximation register, single-slope (SS), two-step and hybrid topologies. Using the suggested equation and data collected over the past ten years, we elucidate the reasons behind the dominance of the column-based SS ADC in commercial products. The proposed FoM is therefore useful for gauging the potential of new architectures and for architecture selection at an early stage of the design process.