Pre-Calculating Ising Memory: Low Cost Method to Enhance Traditional Memory with Ising Ability

Combinatorial optimization always contains many state search operations, which greatly reduce the efficiency of Von Neumann architecture. The Ising chip, expressing the behavior of magnetic spin systems with CMOS circuit, can efficiently support such operations. On the Ising chip, the state search can be carried out for all the spins in parallel. As the Ising chip is mainly SRAM based architecture, we propose Ising memory that enhancing the traditional memory with Ising ability, which can be easily integrated into Von Neumann architecture for both traditional data storage and efficiently solving combinatorial optimization problems. However, due to the non-memory logic for state search operations, directly integrating Ising ability into traditional memory would introduce additional 2× area overhead. To solve this problem, we propose pre-calculating structure to reduce the complexity of the state search circuit. Our proposal helps to reduce the non-memory area overhead to about 0.9× of the traditional memory. Moreover, we have physically designed an Ising memory and tested it with image segmentation problems. Our Ising memory can accelerate the segmenting processing by 26000× with only 0.0001× energy consumption. The experiment result shows that our Ising memory is a low cost method to enhance traditional memory with Ising ability for both data storage and solving combinatorial optimization problems.