Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic

Markov Random Field (MRF) has been adopted to achieve high noise immunity for computing systems in deep sub-micron condition. However, complete MRF designs consume large area overhead, limiting its direct hardware implementation for one-dimensional discrete cosine transform. As a low-cost number representation, stochastic logic can efficiently simplify computing circuits. By combining the two techniques, we present an MRF-based gate group design in order to achieve area and power saving with high noise immunity for stochastic adders used in discrete cosine transform. To validate the performance of our design, we implement an 8-point one-dimensional discrete cosine transform (1D-DCT) system applied the proposed design in 65 nm CMOS technology. Simulation results show that the proposed design can achieve 7% higher noise-immunity with 31% area-saving for stochastic adders and 52% power-saving, compared with the area-saving Master-and-slave stochastic 1D-DCT. The proposed design benefits outdoor sensors and biological portable devices dealing with image compression.