Platform PI-PD co-design and validation for power efficient HSIO interfaces

An efficient and effective methodology for platform power delivery and power integrity (PD-PI) co-analysis and design optimization has been developed, for investigating high yield loss, to support SoC validation. Both frequency and time domain results have demonstrated good correlation between simulation and lab measurement. Consequently it enabled quick verifying the root cause and optimizing work-around power delivery fixing solutions, and further provided optimal PD configuration scheme to key customers for their platform design.