Image Compression Using 2D-Discrete Wavelet Transform on a Light Weight Reconfigurable Hardware

This paper presents a hardware implementation of a 2D-DWT on a reconfigurable architecture targeting image processing applications. The architecture is capable of performing various other digital signal and image processing functions such as CORDIC, FIR filtering, 2D convolution and DCT to compute transforms, trigonometric functions etc. In this paper, we present the mapping of a configurable 2D-DWT algorithm using convolution method with separable filter approach having filter length upto 8 taps on the reconfigurable architecture hardware. The reconfigurable hardware architecture mapped with 2D-DWT is ported onto an FPGA that has a frequency of operation of 37.26 MHz. For a 1-level decomposition, the number of clock cycles are 496 per 8x8 block of the NxN image with a total clock cycles equals 31N
²
/4 with 75% compression and can be further improved by computing higher levels of decomposition of the 2D-DWT.