Design optimization InGaAs/GaAsSb-based heterojunction Gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET)

The InGaAs/GaAsSb-based heterojunction gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET) has been designed and optimized by Silvaco ATLAS technology computer-aided design (TCAD) simulators. The proposed device has a GaAs
_0.35
Sb
_0.65
-based p-doped source, In
_0.7
Ga
_0.3
As-based i-doped channel and In
₀
.
₇
Ga
_0.3
As-based n-doped drain. The gate-to-drain length (L
_GD
), height of source region (H
_source
) and epitaxially grown thickness of channel (t
_epi
) was selected as design optimization variables of InGaAs/GaAsSb-based GAA A-TFET.