Sensing voltage compensation circuit for low-power dram bit-line sense amplifier

As the DRAM process technology scales down, the offset voltage caused by the V
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mismatch between the Latch Transistors of Bit-Line Sense Amplifier (BLSA) tends to increase further. This offset voltage eventually leads to a data read failure by reducing the sensing voltage. To solve this problem, various types of offset cancellation BLSA have been studied. In addition to the offset voltage, the sensing noise between adjacent bit lines is another major cause of reduced sensing voltage. The solution to this problem is also necessary as the minimum feature size of the DRAM cell decreases. In this paper, we propose a Sensing Voltage Compensation (SVC) circuit for DRAM BLSA that can solve both problems simultaneously.