Hardware design of cryptographic accelerator

The goal of this paper is representation of computing unit focused on implementation hardware cryptography accelerator. After analysis of assigned problem, there are next chapters dedicated to available solutions, comparison of them, the issues of cryptography and computer security, FPGA device in which the designed solution is verified and tested, the chapters dedicated to cryptography algorithm RSA. Chapters of synthesis have the specifically implemented and designed solution in programming languages of lower and higher level. In evaluation and conclusion chapter there are measurements on software and hardware level and comparison among them.