An approach to automatic test generation for verification of microprocessor cores

In connection with the architectural complexity of modern multi-core structures, more than 60% of the design resources are spent on verification during the development of the processor. Automatic generation of tests is often used to increase test coverage and reduce overall test time. This paper describes the technique of development of a system-level tests generator used for multicore structures verification. In the suggested approach, source code of the tests is constructed by using combinatorial techniques. All possible combinations of instructions, situations, and dependencies are sorted taking into account the constraints that are direct the tests to check certain situations and also exclude the possibility of generating infinite cycles. The proposed approach to verification of multi-core structures allows increasing the efficiency of testing.