2.65 GHz 340 W dual internally matched FETs for compact doherty power amplifiers

This paper presents dual IMFETs for a compact DPA based on pre-matching networks and GaN-HEMT bare-dies. For impedance matching networks from very low optimum load and source impedances of the high-power transistor bare-die, input and output pre-matching networks using MOS capacitors and multiple bond-wires are employed for two high-power GaN-HEMT bare-dies, which are used for the carrier and peaking amplifiers of the compact DPA. Additional matching networks on small substrates are implemented for the matched source and load impedances of 50 since the optimum input impedance and the complex conjugate of the optimum load impedance can be used to partially match the pre-matching networks. At the same time, the second harmonic impedances are terminated to the optimal regions using the sufficiently large capacitances of the MOS capacitors and bond-wire inductances of the input and output pre-matching networks. The dual IMFETs have a total size of 23 × 35 mm
²
. The DPA module was implemented by adding an input splitter and Doherty load network to the dual IMFETs. The DPA exhibited a drain efficiency of 44% at an average output power of 49.8 dBm, using a down-link LTE signal having a center frequency of 2.65 GHz, a channel bandwidth of 10 MHz, and a PAPR of 6.5 dB.