JICG MOS transistors for reduction of radiation effects in CMOS electronics

In order to improve the total ionizing dose (TID) and single event upset (SEU) radiation tolerance of bulk CMOS technologies we applied two constructive measures. TID induced source-drain leakage is suppressed by a junction isolation (JI) of the source drain regions using silicide blocked well regions. To decrease the susceptibility against SEU we introduced a redundancy on transistor level, where each MOS transistor is replaced by a stack of two spatially separated single transistors which share a common gate (CG). The radiation hardness and device performance of the novel JICG MOS transistors fabricated in IHP's 250 nm SGB25RH technology were evaluated.