Investigation of low temperature performance in heterostructure strained-Si n-MOSFET

This paper explorers the low temperature performance study of heterostructure strained-Si device using analytical electron mobility modeling. A long channel device reported in literature and equivalent scaled short channel device have been considered for investigation. The performance of these devices are inspected in terms of transconductance, output characteristics and peak mobility with good agreement of experimental validation. Moreover, the change in threshold voltage with lowering in temperature has been presented with a comparison of Si and strained-Si devices. The variation of ON and OFF state current have also been presented. The overall performance of strain device indicates itself to be a potential candidate for low temperature application in rapid scaling era.