Physical implementation of low power SoC chip based on SEC 28nm FDS

Low Power technologies are increasingly important, driven by the mobile device, IoT market, and the energy-saving. FD-SOI technology becomes more popular after few products successfully introduced in this process. It shows more possible methods to reduce the chip power consumption. This paper presents physical design of a Low Power SoC chip. The FD-SOI benchmark experience and customized IP design experience help to reduce the implementation schedule. We have developed dedicated 28nm FD-SOI IPs: USB2.0, MIPI DPHY, Audio CODEC, and the Low-power Memory. The physical implementation of the chip has been completed within 2 months.