Distributed arithmetic architectures for FIR filters-A comparative review

Finite impulse response (FIR) filter is an influential block in various signal processing applications. The complexities in VLSI implementation of FIR filters is dominated by the number of multiply and accumulate (MAC) operations. Distributed Arithmetic (DA) is an alternative technique where the MAC operations can be replaced by a series of look-up tables and addition operations. FIR filter based on DA are computationally efficient because of high degree of mechanization involved in the implementation of MAC operations using DA. Many reconfigurable and non-reconfigurable FIR filter architectures can be developed using DA. This paper reviews the existing FIR filter architectures based on DA. LUT based DA and LUT-less DA are the significant methods in the implementation of non-reconfigurable filters. This brief summarizes the area and power reports of the existing non-reconfigurable FIR filter architectures based on both LUT based DA and LUT-less DA. One dimensional and two dimensional systolic DA based architectures for FIR filter implementation are also briefed. DA based adaptive FIR techniques are explained. This paper presents the comparative results of FIR and adaptive FIR filter architectures in terms of area, power, area-delay product, minimum cycle period and energy per sample. This survey can form a basis for further research on DA based FIR filter architectures.