SCBench: A benchmark design suite for SystemC verification and validation

SystemC has become a de-facto standard hardware modelling language in the semiconductor industry, enabling early exploration of design spaces and verification at a higher level of abstraction. It is both important and necessary for researchers to evaluate their new verification approaches and algorithms quantitatively. This paper presents SCBench, a comprehensive suite of benchmark designs for SystemC verification and validation. SCBench consists of 38 well-written representative behavior-level SystemC designs, which have been selected carefully from various application domains, such as CPU architecture, security, network, and artificial intelligence. The benchmark covers most core features of SystemC language. SCBench is freely available online to all researchers.