Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wires

Electromigration (EM) remains the top killer of copperbased damascene interconnects in 10nm and beyond technologies. On-chip power/ground (P/G) networks are most vulnerable to EM failures due to large and unidirectional current flows, thus proper sizing and even routing of power grid networks are critical for the full-chip EM sign-off. In this paper, we propose a new P/G network sizing technique based on recently proposed fast EM immortality check method for general multi-segment interconnect wires and physics-based EM assessment technique for fast time to failure analysis. We first show that the new P/G optimization problem subjected to voltage IR drop and new EM constraints can still be formulated as a sequence of linear programming (SLP) problem. The new optimization will ensure that all the wires will not fail if all the constraints are satisfied. To consider EM-induced aging effects on power supply networks for the target lifetime and mitigate the over-conservation of the first optimization formulation, we further propose an aging-aware P/G optimization method, which allows some short-lived wires to fail or to age and optimizes the rest of the wires considering resistance increase of those failed wire segments. In this way, the P/G networks can be optimized more effectively and become more robust and aging-aware. Numerical results on a number of IBM and self-generated power supply networks show that the new approach can effectively reduce the area of the network while ensuring immortality or improving target lifetime of all the wires, which is not the case for the existing current density constrained optimization method.