A post-processing methodology to improve the automatic design of CMOS gates at layout-level

The main goal of many recent works is to generate small transistor networks and optimize cell layouts automatically. However, when networks are generated by some given methodology, the layout aspect is not considered, and consequently, the layout quality may be affected. The key point of this work is to analyze the transistor network generated by any technique and apply the proposed methodology aiming to improve the final cell layout. Previously works are able to optimize only series-parallel (SP) networks while this work is able to optimize the SP and non-series-parallel ones. To do that, the proposed post-processing methodology performs a smart reordering in the switches of the network intending to produce better results during the automatic layout design. The performed cell set demonstrates that the post-processing methodology is able to produce layouts, in comparison to the original ones, that reduces geometric aspects as area (2% in average), contacts (2.5%) and wirelength (0.8%), and improves some electrical aspects, like leakage (1.74%) and switching power (2.6%).