Pipelined-scalable FFT core with optimized custom floating point engine for OFDM system

Pipeline FFT is a specified class of processors for DFT computation utilizing optimized algorithms. The main characteristic of the FFT is its ability of continuous processing of the incoming data samples. Input data samples are continually fed through the processor. The obvious advantages of Floating point number system are that it has good dynamic range and precision, less design complication of analyzing fixed point word lengths, which includes scaling operations (i.e. dealing with different Q format conversions) to avoid overflow. Applications such as Digital signal processing, imaging radar, audio and precision scientific computing inherently require a high dynamic range so that floating-point support for such systems is necessary. The design uses R2SDF Radix-2 Single path Delay Feedback DIF-FFT which is more effective because it stocks the butterfly output in feedback shift registers. The Design of 1024 point 12bit custom floating point FFT was coded in Verilog HDL implementation results were obtained for spartan6 FPGA (xc6slx45t-3fgg484) Maximum Frequency achieved of the design was 110.290MHz. FFT Validation was done using MATLAB reference model, test vectors are generated from MATLAB. A soft core implementation was done using Microblaze on Artix-7 35T FPGA evaluation kit to validate its working on the hardware.