Design of reconfigurable LFSR for VLSI IC testing in ASIC and FPGA

This paper focus on the design of a reconfigurable Linear Feedback Shift Register (LFSR) for Very Large Scale Integration (VLSI) Integrated Circuit (IC) testing. The advancement in VLSI technology have made chip testing more complicated which has lead to the popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows in-built chip testing with the help of an additional hardware structure inside the circuit. The test patterns are not applied by ATE but are generated by inbuilt testing circuits. Thus it reduces testing costs considerably. LFSR is commonly used as a test pattern generator since it is more efficient than binary counters. Reconfigurable LFSR can be used as the test pattern generator inside Logic BIST to improve the fault coverage of IC testing. As per requirement it can be configured to generate maximum length sequence or any length patterns depending on the feedback polynomial provided. It increases the random patterns generated that are applied as test vectors. The proposed LFSR architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 64) programmable LFSR structures is synthesized in Xilinx Spartan 3E for implementing LFSR on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete LFSR are implemented. All the designs are synthesized for ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable designs are analyzed for speed, power and area.