Radix-10 multiplier implementation with carry select adder using Verilog

Multiplier play important role in various applications and in recent years there is an increase in multiplication applications, thereby raising the need for multiplier that performs faster multiplication. This paper presents the implementation of multiplier using radix-10 approach using Verilog. For implementing the multiplier will using a modified BCD adder with pre-correction step and Carry Select adder with BEC. A BCD precorrection adder is used while the calculation of multiplicand multiples and CSLA with BEC is utilized while the addition of partial products. CSLA with BEC design gives a parallel path for carry propagation, thus reduce the time required to carry to propagate through adder. A radix-10 approach uses for multiplier digit recoding. The paper gives the design and implementation of 16-bit multiplication unit. The necessary prerequisites for multiplier designs are High speed, low power consumption and compact area.