A novel multiple dies parallel NAND Flash Memory Controller for high-speed data storage

NAND Flash Memory is frequently used in digital electronic products presently by right of its stable, energy-saving, high shock resistant and mini size. It is playing a significant role as high-density static memory storage. However, the timing sequences of NAND Flash Memory is too complex for user to operate. Nowadays, multiple dies parallel structure are gradually applied into the storage system to improve data access speed. In this paper, to apply the concept of pipeline technology and parallel processing to the whole system, we suggest designing multiple dies NAND Flash Memory Controller architecture. This design is different from the existing technology, which using a single controller to operate multiple dies NAND Flash Memory concurrently. Another important feature is that the double data buffer technology is adopted by the NAND Flash Memory controller, which can promote the performance of the design. The experimental results based on FPGA demonstrate that our controller can operate NAND Flash Memory correctly to meet the requirements of functionality and show the excellent performance that the speed of read is 626MB/s and the speed of program is 50.8MB/s at system clock frequency of 50MHz. From this, we can see that the proposed design implement high-speed data storage.