Multi-Vth technique based on potential critical paths for NBTI effect and leakage tradeoff

NBTI-induced PMOS transistor aging has become an important influence factor of the circuit reliability in the current technological dimension. In this paper, Multi-Vth technique based on potential critical paths for NBTI effect and leakage tradeoff is proposed. The potential critical paths can be found at the preset timing margin and the critical gates in the potential critical paths can be replaced with the low threshold voltage type through the optimization algorithm mentioned in our paper. The experimental results on ISCAS85 benchmark circuits at 45nm node show that the after-aging delay improvement rate is up to 12.95%, which is obviously better than the current multi-threshold voltage scheme. Simultaneously, the leakage power overhead is less. Our method is more effective for the larger circuit in the anti-aging aspect.