Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm

This paper discusses SRAM scaling beyond the 5nm technology node and highlights the fundamental scaling limits due to FinFET and Gate all-around (GAA) technology. To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the cell height. However, limited scaling benefits can be achieved in FinFET and GAA technology. Therefore, a novel vertically stacked lateral nanosheet architecture using a forked gate structure is proposed showing superior performance and area scaling compared to FinFET and GAA devices. Moreover, limited additional processing complexity can be achieved. The Fork architecture allows 20% SRAM area scaling at isoperformance and 30% performance increase at iso-area compared to FinFET beyond 5nm technology node.