I. Introduction
Testing and verification are very important steps in designing complex systems. Many verification techniques use a formal specification that describes admissible behaviors of a system during its execution in a mathematically unambiguous manner [1]. For this reason, specifications are expressed using appropriate logics, and Signal Temporal Logic (STL) has emerged as a rich specification language for describing continuous-time systems [2]. Traditionally, specifications are formulated by expert designers in a tedious and error-prone process. More recent methods involve learning the specifications directly from the execution traces of systems.