Unified and efficient power integrity impedance target flow for flexible PCB design

The modern communication system, data center and electronics devices deign, are facing increasing challenges in power delivery network design, besides the well-known signal integrity design challenges. In order to make sure the designed product works well to meet design specification, normally platform design guideline will be provided from System on Chip (SoC) suppliers to OEMs or ODMs before OEMs/ODMs product design phase. After the SoC have been well designed for power integrity by SoC suppliers in terms of power delivery network, conventionally a customer reference board (CRB) with a fixed PDBOM and an assumed stack-up which meets the targeted performance at the known worst case scenario will be provided to the OEMs or ODMs as reference design. Nowadays, one SoC will be widely used in many different products. For example, Intel Ultra product line is used for Microsoft Surface-pro product on any layer, u-via of 10-layer HDI motherboard with performance oriented. It is also used for China Technology Eco-system (CTE) low-end laptop on 6-layer, through hole via motherboard with cost optimized design. The customer reference board with a fixed PDBOM and an assumed stack-up in Platform Design Guideline (PDG) could not cover all OEMs/ODMs product design specification requirement, like the performance oriented product or the cost optimized product. And it results in many out of guideline (OOG) designs in the industry with the same SoC. In order to meet design specification of OOG products, the OEMs/ODMs have to invest significant PI resource to re-do the PI design to make sure their products' success. Unified and Efficient Power Integrity Impedance Target Flow (UEPI Flow) provides the flexibility to OEMs/ODMs in designing their products with freedom of doing trade-off among performance, cost and schedule. With provided SoC package MCP (Model Connection Protocol) PI model and coengineered within a commercial EDA tool, OEMs/ODMs can verify their product PI design by this flow flexibility and efficiency. It can help to reduce OEMs/ODMs product design resource, shorten product design phase and increase product design quality.