Dynamic power optimization using look-ahead clock gating technique

Main part of power dissipation in real time processors occurs due to dynamic power. Thus to reduce this in digital systems a technique namely clock gating is used. The three most popular techniques are latch-based, data-driven and Auto-Gated FF (AGFF) based clock gating. Here a combination of above techniques namely Look-Ahead Clock Gating (LACG) is presented. Problems such as timing and hardware overheads can be solved using LACG.