An on-chip circuit for timing measurement of SRAM IP

The timing of silicon IPs should be measured before they are integrated into chips. Embedded solutions are needed for timing measurement of silicon IPs. This paper introduces a circuit design for timing measurement of SRAM IP. A new circuit is designed for the measurement of setup time, hold time and access time. This circuit is fabricated in SMIC 130nm CMOS technology. Testing results show that the proposed circuit can achieve an accuracy of 9.0ps with a good linearity. The timing measurement circuit has configurable capability and could be applied to the timing measurement of SRAM IPs.