Efficient hardware realization of digital image decoder

In this paper, efficient hardware realization of digital image decoder, has been described. Each block, the proposed image decoder consists of (entropy decoder, decoder probability estimator, dequantizer and inverse subband transformer), has been developed with intention to optimize the hardware architecture and reduce the amount of used logic and memory resources in separate blocks themselves, as well as in the entire image decoder. The proposed realization has been verified by implementation within a low cost FPGA chip.