An efficient hardware implementation of vector-based odd-even merge sorting

Sorting is one of the basic computational operation that has an immense impact on the performance of the system. Since the past few decades, sorting algorithms have been studied extensively in the field of hardware engineering and real-time operating systems. The efficiency of an application depends on the usage of a sorting algorithm. In this article, we have compared various sorting algorithms on basis of time complexity. We propose a vector-based parallel odd-even merge sort, which has worst-case time complexity less than that of O(n). This sorting algorithm is first designed and simulated in Matlab. We then implement bit-true, cycle-accurate and high-throughput architecture for the same algorithm on Xilinx Virtex-7 V C707 field programmable gate array (FPGA) emulation kit.