Low-power dual-modulus frequency divider by 4/5 up to 13-GHz in 0.13μm CMOS

This paper presents a dual-modulus flip-flop-based frequency divider with programmable division ratios by 4/5 designed in a 0.13 μm CMOS technology. The divider is based on a modified CML D-latch topology, for high speed operation and a low power consumption. The AND gates used for realization of dual-modulus operation are integrated directly into the D-latches to achieve low power consumption and minimum gate delay. This modified circuit topology is verified in measurement, exhibiting operation up to 13 GHz. A broadband output buffer is included to drive a 50 Ω measurement equipment. The divider by 4/5 including a 50 Ω buffer draws 21 mA from a single 1.5 V supply. The active circuit including buffer consumes a chip area of only 130 μm × 72 μm.