A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration

A scaling-friendly and PVT-robust pipelined SAR ADC reusing the first-stage comparator as a regenerative residue amplifier is proposed in this work. A low-power self-timed gain control block is combined with a mixed-signal background calibration to ensure a stable amplifier gain across PVT variation. A 130nm CMOS prototype achieves a peak Walden FoM of 9.2 fJ/conv-step and a Schreier FoM of 172 dB.