I. Introduction
With the advancements in the technology, clock rates have increased to giga-hertz ranges, so signal integrity has become a critical issue in many high speed design applications. Signal integrity problems are getting more severe and posing several challenges to the designers depending on the applications. The projections of Semiconductor Industries Association (SIA) and International Technology Roadmap for Semiconductors (ITRS)-2001[1] have predicted that the future on-chip clock frequencies is increasing at a slightly diminishing but still a growing rate for the next decades. So, it becomes necessary to solve the problems pertaining to signal integrity issues to obtain optimum yield. In today's signal integrity analysis, transmission line theory is the most useful concept used. There is a need to master the signal integrity problems and implement an efficient design approach by embedding new rules, technology and analysis methods to address the problems of signal integrity. So it is required to understand the basic or fundamental principles of signal integrity at intuitive level and its impact on the overall performance of the system. Signal integrity [7] in its broad sense is referred as: all the problems that arise in high speed applications due to its interconnects i.e. the properties of interconnects, that interacts with the input signal's voltage and current waveforms affects the performance. For most of the applications, signal integrity effects begins at clock frequencies above 100MHz or rise times shorter than 1ns, which is called as high frequency or high speed regime. Signal integrity can cause many problems such as ringing, reflections, ground bounce, attenuation, near and far end crosstalk, switching noise and capacitive loading. Signal integrity problems prevent the correct operation of a high speed designs. For all the high speed applications, a system level simulation and verification are to be performed in order to accurately predict signal integrity effects. The signal integrity analysis of high-speed designs requires: interconnect models are valid over a wide range of bandwidth.