Area-efficient polynomial modular multiplication over GF(2∧n) and application to AES

Due to low masking-complexity property of the addition chain, it has been widely researched for evaluating the S-boxes in the recent literatures. This paper summarizes four main addition chains developed for the AES S-box in the existing literatures and chooses the most area-efficient addition chain. To further reduce the masking complexity, this paper proposes an improved algorithm for evaluating the polynomial modular multiplication. Based on the proposed algorithm, the non-linear multiplier, the square multiplier and the constant multiplier are developed separately to implement four different addition chains. To evaluate the performance, these addition chains are modeled with the Verilog, synthesized with the Synopsys Design Compiler and compared with each other. The comparison results show that the addition chain with less non-linear multipliers and square multipliers has less area. According to the comparison results, this paper chooses the most area-efficient addition chain to implements the whole AES. The research in this paper lays the foundation for the high-efficient higher-order masking scheme of the block cipher algorithm.