Design of optimized MAC unit using integrated vedic multiplier

Multipliers are core components of most of the digital signal processing algorithms which lie in critical delay path and decide performance of any algorithm. Over the years various approaches have been proposed to reduce the computational overhead of conventional multipliers. Vedic mathematics has been one among them. In this paper, a novel multiplier unit is proposed which integrates the advantage of each of the sutras. “Sampoornam” alias “Absolute vedic” multiplier is designed to have a specialized logic unit that decides which multiplier is to be used for optimum results based on the types of input, improving efficiency. The proposed multiplier Sampoornam is used for designing a 4-bit Multiplier accumulator unit (MAC) unit and is extended up to 64-bit using Vedic scaling technique. Sampoornam is comparatively time efficient than the present day multipliers such as (a∗b) algorithm, Booth and Wallace. The 4-bit MAC unit developed using sampoornam has 25 % reduction in time delay compared to MAC developed using Wallace multiplier. Similar trend is observed as the number of bits is increased.