Memory testing and fail bitmap generation for fault correlation

Static Random Access memory (SRAM) has a dense and regular layout structure with Bitlines (BL) and complementary Bitlines (BLN) running simultaneously along with power and ground lines. It can result in fabrication failures during wafer processing. Memory test algorithms read and write specific data in particular sequence so that maximum possible functional failures could be detected during testing. Many System On Chip (SoC) designs often make use of embedded memories. Low memory yield can restrict overall device yield in such scenario. Memory electrical test results are used for correlating fail bitmap patterns with possible process defects. Hence, it becomes necessary that proper fail bitmaps are recorded during testing. This is an essential step in failure analysis to improve the process yield. This paper discusses memory testing methodology for measuring dc parameters, selection of test algorithms, automatic generation of wafer maps with pass/fail bin information and fail bitmaps.