Implementation and comparative analysis of double gate low power multiplexers using dynamic logic styles

This paper presents the Implementation and Comparative Analysis of Double Gate Low Power Multiplexer using Dynamic Logic Styles. The main design goal for VLSI designers is to optimize power. In Conventional CMOS with single gate terminal short channel effects and leakage problems occur. This can be overcomed by moving on to new technological era i.e., Double Gate Technology. Multiplexers are used to share several input devices concluded in a single device. Multiplexer is a digital device with 2N input lines with N selection lines giving out single output. Logic styles are which to represent logical functions in different ways that to give out better device parametrically. Dynamic logic styles that are used in Conventional CMOS for optimizing power, area, delay etc. Different types of dynamic logic styles are used in this paper like Complementary CMOS (C2 MOS), DCVS Logic, Pseudo NMOS, Domino Logic, Low Power Feed through Logic. The present proposal is to implement multiplexer using both conventional & Double Gate Technology by incorporating different dynamic logic styles. The performance parameters are compared between Conventional Multiplexer and Double Gate Multiplexer which are implemented using dynamic logic styles. This gives a rich parametrical space. The Implementation and Simulation of Low Power Multiplexer using DSCH 2.6F Microwind Tool using 120nm technology.