Testing of FIFO buffer of NoC router using BIST

Systems on-Chip (NoC) has created as a promising answer for on-chip interconnection in SoC because of its adaptability, reusability, adaptability and parallelism. It is important to identify and rectify the fault in the Network on Chip. Testing is an important process to find and rectify the fault in Network on Chip. In testing, FIFO buffers produce high throughput gain as well as reduce latency. BIST (Built in Self-Test) is used for testing the routing process. BIST strategy is used for testing the NoC interconnect network and investigates if the strategy is a suitable approach for the task. The intention is to custom BIST to detect faults and to be able to pinpoint the location of each defect and finally use this information to reconfigure the architecture. Periodic testing of buffers avoid accumulation of faults and also allows test of each location of the buffer. The periodic testing of FIFO buffers do not have much effect on the overall throughput of the NoC, except when buffers are tested also frequently and this implementation is done in Xilinx.