Implementation and analysis of power reduction techniques in charge transfer sense amplifier for sub 90nm SRAM

This paper describes the implementation and analysis of different low power reduction techniques in charge transfer sense amplifier based on 90nm CMOS technology. The charge transfer sense amplifier has been characterized to find out their performance in terms of power dissipation. The Forced Stack technique shows a good improvement in leakage power dissipation of about 23.82 μW as compared to Sleepy Stack (41.313 μW), Variable Body Biasing (38.805 μW) and Footer Stack (29.947 μW) techniques. It has been also observed that the CTSA shows an overall reduction in leakage power dissipation up to 35.014 μW.