Reduced-memory high-throughput fast-SSC polar code decoder architecture

Polar codes have been selected for use within 5G networks, and are being considered for data and control channel for additional 5G scenarios, like the next generation ultra reliable low latency channel. As a result, efficient fast polar code decoder implementations are essential. In this work, we present a new fast simplified successive cancellation (Fast-SSC) decoder architecture. Our proposed solution is able to reduce the memory requirements and has an improved throughput with respect to state of the art Fast-SSC decoders. We achieve these objectives through a more efficient memory utilization than that of Fast-SSC, which also enables to execute multiple instructions in a single clock cycle. Our work shows that, compared to the state of the art, memory requirements are reduced by 22.2%; at the same time, a throughput improvement of 11.6% is achieved with (1024, 512) polar codes. Comparing equal throughputs, the memory requirements are reduced by up to 60.4%.