A 28 GHz transceiver chip for 5G beamforming data links in SiGe BiCMOS

This paper presents a 28-32 GHz transceiver chip architecture in SiGe BiCMOS to meet the requirements of 5G phased-array communication links. An asymmetric design is employed for the transmit and receive paths to deliver an output P1dB of 8 dBm in TX mode and to achieve an input P1dB of 0 dBm in RX mode. The chip can operate with an external LO at 10-16 GHz and 20-28 GHz with the use of an on-chip doubler option. All switches on RF, LO and IF paths are implemented using SiGe HBTs for low loss and wideband operation. An on-chip elliptic filter is implemented in the TX path to reject the upconverted image and LO leakage to meet spectral mask requirements. The chip was tested in the TX mode with an 802.11ad MCS-10 waveform and achieves 3.9% EVM at 3 Gbps physical rate.