I. Introduction
In parallel architectures with local caches, cached values can become stale. Therefore, it is imperative that the system guarantees shared memory correctness by ensuring that it correctly implements a memory consistency model (MCM)-the formal model that determines what value a read should return [1]. An integral component of enforcing an MCM is the cache coherence protocol (CCP), which is responsible for making writes visible to other caches in an order that is consistent with the MCM.