Design and simulation of low power, high gain and high bandwidth recycling folded cascode OTA

This proposed work explains the design and simulation of a recycling folded cascode OTA based on the conventional folded cascode architecture. The benefit of recycling structure is that it delivers an enhanced performance when compared to that of a conventional folded cascode structure. The enhancement in gain, bandwidth and reduction in power for the recycling structure is achieved by reusing the idle transistors in the signal path. A 32nm CMOS process is used in HSPICE tool for simulations. When compared to the conventional folded cascode, the recycling folded cascode OTA achieves 4.5dB improvement in gain, 430MHz enhancement in bandwidth and 67μW reduction in power with the same load capacitor of 150fF. The proposed modified recycling OTA achieves 3.3GHz improvement in bandwidth and 467 μW reduction in power compared to existing recycling folded cascode OTA.