FPGA Implementation of Image Splitting and Enlarging

Splitting the real time image of size P x Q into four enlarged image blocks without zooming. Each splitted image blocks are interpolated to the dimension of the original image without blurring and display image in four different screens. The design is implemented using the simulink, system generator module and finally on the FPGA. In this paper, techniques for splitting and enlarging an image are implemented on FPGA, simulated on Modelsim 6.3f and system generator model also presented.