A high speed parallel timing synchronization algorithm for 16QAM

The paper presents an efficient parallel timing synchronization algorithm structure, which is suitable for high speed communications demodulation system and easy to implement on FPGA platform. First, a new parallel timing synchronization structure is displayed. Wherein the proposed parallel structure make up of a feedback loop based on the farrow interpolation filter, Gardner algorithm and the numerically controlled oscillator (NCO) controller. In addition, the parallel implementation structure of these modules has been studied. Especially, the principle based on the sign bit decision is employed in parallel NCO algorithm. By this feedback loop, we can get the best symbol points after timing synchronization. The simulation results show that the entire parallel timing synchronization algorithm not only can correct working, but also the system performance loss does not exceed 1dB.