Area efficient dataflow hardware design of SAO filter for HEVC

This paper presents the Area Efficient Dataflow Hardware Design of Sample Adaptive Offset filter (SAO) for High Efficiency Video Coding (HEVC). The proposed SAO filter architecture is designed to utilize least amount of resources which minimizes chip area and yields high synthesis frequency as is required for 4k×2k decoding/encoding based applications. The proposed filter is designed to work with a 64×64 de-blocked Coding Tree Unit (CTU) block which is enhanced to 66×66 to include the boundary pixels. The proposed SAO filter is based on the sequential access of pixels obtained from DBF using a control path. These values are filtered and mapped to 64×64 CTU and finally written in memory. The proposed SAO filter design is implemented on FPGA platform (Virtex-6-lx240T). The synthesized frequency is obtained as 100MHz in ASIC platform. The chip layout area is 15585.328 μm
²
and gate count is 5k. The resource consumption is less as compared to literature works.