Triangular CNT bundles as VLSI interconnects

The performance of coupled VLSI interconnects depends on their coupling capacitance and the dielectric medium surrounding them. However, the idea of designing the geometry of CNT bundles to optimize the coupling capacitance is not considered till now. So, in this paper, we model triangular CNT (T-CNT) bundles as VLSI interconnects, for the first time. Factors that reveal the performance of interconnects like propagation delay, crosstalk delay and power dissipated by the interconnects, are simulated in this paper. We do the performance analysis of T-CNT bundle interconnects and conventionally modeled square type CNT bundle interconnects. Upon comparison of the above said metrics, it was found that T-CNT bundle interconnects performed better.

I. Introduction

Scaling down of VLSI circuits to meet the Moore's law is continuously posing fresh challenges of their performance and reliability. New materials and hence new processes are being introduced to meet the requirements of ultra high speed and low power circuit elements in VLSI. Interconnects form a major portion of VLSI chips and hence their performance is of utmost importance. Transistor scaling lead to performance enhancement coupled with low power operation. But, interconnect scaling leads to performance bottlenecks in terms of delay and power dissipation [1]. Due to electromigration of Copper interconnects at 22 nm technologies and beyond, alternate materials like Carbon nanotubes are being introduced as interconnects [2]. Since the last decade, many people have worked on modeling, simulation and fabrication of CNT interconnects [3]–[5]. Both metallic SWCNTs and MWCNTs are proposed as local, intermediate and global interconnects [6]. Mixed CNT bundles, which are more realistic in growth point of view, were studied by us earlier [3], [7].