An early-EMI analysis method for the LPDDR interface

In this paper, an accurate noise level estimation technique in the design stage for LPDDR system is presented. In order to predict the system performance, the equivalent circuit based simulation model and the input parameter range for the sweep simulation is required. The package and board are modeled by using RLC equivalent circuits. The input parameter range is determined by investigating the characteristics of the existing products. The noise level of the LPDDR system in the mobile platform can be estimated by using equivalent circuit model and input parameters. It is shown that noise level at the input pad of the receiver using the proposed method has a good agreement with S-Parameter based model within less than 8dB.

I. Introduction

In the current fast-changing and dynamic consumer market, we are witnessing a drastic increase in the operating speed of devices which is aided by rapid changes in semiconductor processes [1]. This phenomenon is very visible in the smart phone market where the usage of Low Power DDR(LPDDR) memory requires several GBps/pin for data transfer [2]. A cellular phone is integrated with many electronics parts such as chips, antennas, and battery with multiple interactions between each sub-part. The main processing block of the smart phone is the Application Processor (AP) which in turn consists of multiple smaller sub-blocks which operate in different modes. Hence, each of the sub-blocks can be an aggressor or victim in different scenarios of operation. Due to these large numbers of blocks operating, it is very important to find the biggest noise source generator in the system and also, in turn the most sensitive blocks for external and internal noise disturbances. The field intensity levels can be measured by a near-field scanner with the magnetic field related to current consumption and flow in the mobile system. As shown in the figure 1, measured near-field scanning results of the LPDDR AP-DRAM interface is the biggest noise source in the AP chip because it has multiple data lines and a very high operating frequency [3]. In order to accurately estimate the performance, both the on-chip circuit and off-chip models such as the AP package and the system PCB model are needed. However, the circuit designer cannot get access to the required package models in the on-chip design phase. To reduce Turn-Around-Time(TAT) and cost for the design and revision of post tape-out EMI related bug-fixes, it is important for the designer to know the dominant factors and parameters to predict system performance. Therefore, the characterization of the noise level of the LPDDR is very important to future analysis for EMI related system level simulation. Once these variables and system model are determined, the system performance can be evaluated by parameter sweep simulations. In this paper, we propose a pre-design phase accurate noise level estimation method of the LPDDR system with focus on the mobile applications. To achieve this work, we choose an existing system and apply the design flow. We then compare the noise characteristics of the existing system and equivalent circuit model based system. If there is good level of match between the existing and circuit model based systems, the modeling methodology is validated and can be used for future products before the parameters such as an IO Power Delivery Network(PDN), a package model, and a PCB model are designed and released and hence, provide valuable guidance to designers in design phase. Figure 1.

Measured field intensity level by near-field scanner.

Figure 2.

Overall LPDDR system.

Figure 3.

Circuit model for the board.

Figure 4.

Z11 curves using the extracted RLC values (, L:54pH, C:45uF) and S-parameter.