FPGA-Based implementation of a high resolution and high carrier frequency pulse-width modulator

Mutual limitations for base clock frequency, carrier frequency and resolution for standard pulse-width modulator (PWM) are described. A new adjustable compact implementation of the enhanced digital PWM-modulator similar to standard PWM but without its limitations is explained. The proposed algorithm allows 16 bits resolution and more with the carrier frequency being as high as desired (up to the system clock frequency) and base clock frequency remains low. This algorithm has been implemented using the standard field-programmable gate array (FPGA) and successfully tested within motor control application.