I. Introduction
The current trend of down-scaling in transistor sizes poses an increasingly complex challenge for digital system designers. The additional available logic capabilities enable the user to map even more complex devices onto same sized silicon. Especially in the area of Field Programmable Gate Arrays (FPGA), the shrinking transistor sizes provide tremendous advancement in the number of configurable elements. Contemporary high-end FPGAs provide more than 3.7 million LUTs (Xilinx UltraScale+ [1]) together with dedicated processing hard macros and large memory blocks. The high logic density also increases the problem of heat dissipation. Regions with higher switching activity might turn out as specific hot-spots, whereas other regions might not have any relevant contribution to self-heating. By monitoring these hot-spots, the temperature can be adapted, e.g., by frequency scaling [2].